High-Level System Modeling: Specification Languages describes the state-of-the-art in specification formalisms in electronic design. The book provides an overview of object-oriented methodologies. It goes on to highlight several formalisms such as VSPEC, ESTELLE, SDL and LOTOS with methods that map their semantics to simulatable or synthesisable VHDL. High-Level System Modeling: Specification Languages is the essential update for researchers, design engineers and technical managers working in design automation and circuit design.