VHDL is the most widespread standard for hardware description. From its initial applications in simulation and ASIC description, VHDL is now being used in a wide range of applications at all levels, from system down to gate. The applications, which include synthesis and formal proof, make VHDL a design support tool as well as a deliverable. The use of VHDL implies a new approach to design. The VHDL Designer's Reference offers engineers and students practical help in addressing real problems encountered when implementing and using VHDL in their companies or research laboratories. It is thus a valuable reference for all practising designers. Intended for the experienced designer, VHDL Designer's Reference discusses modeling issues, design methods, efficiency tricks and portability traps. It also compares VHDL with other hardware description languages such as M, Verilog, and UDL/I. This complete reference provides a resource to help improve the designer's use of VHDL.