Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings<br />Author: Warren A. Hunt Jr., Steven D. Johnson<br /> Published by Springer Berlin Heidelberg<br /> ISBN: 978-3-540-41219-9<br /> DOI: 10.1007/3-540-40922-X<br /><br />Table of Contents:<p></p><ul><li>Applications of Hierarchical Verification in Model Checking </li><li>Trends in Computing </li><li>A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon </li><li>An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps </li><li>Automated Refinement Checking for Asynchronous Processes </li><li>Border-Block Triangular Form and Conjunction Schedule in Image Computation </li><li>B2M: A Semantic Based Tool for BLIF Hardware Descriptions </li><li>Checking Safety Properties Using Induction and a SAT-Solver </li><li>Combining Stream-Based and State-Based Verification Techniques </li><li>A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles </li><li>Correctness of Pipelined Machines </li><li>Do You Trust Your Model Checker? </li><li>Executable Protocol Specification in ESL </li><li>Formal Verification of Floating Point Trigonometric Functions </li><li>Hardware Modeling Using Function Encapsulation </li><li>A Methodology for the Formal Analysis of Asynchronous Micropipelines </li><li>A Methodology for Large-Scale Hardware Verification </li><li>Model Checking Synchronous Timing Diagrams </li><li>Model Reductions and a Case Study </li><li>Modeling and Parameters Synthesis for an Air TrafficManagement System</li></ul>